Semiconductor integrated circuit for a stable constant delay time

ABSTRACT

A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit, andmore specifically to a delay circuit thereof.

In conventional semiconductor integrated circuits, a delay circuit isinterposed between two circuit systems so as to adjust timings, forinstance. The delay circuit as described above is usually composed oflogic gates for generating pulse signals or timings between two signalsand activated on the basis of a single supply voltage.

In the conventional delay circuit, however, in case the supply voltagefluctuates, since the charge and/or discharge time of parasiticcapacitances of the logic gates fluctuates, there exists a problem inthat the delay time also fluctuates, as shown in FIG. 1. In the case ofa SRAM (static RAM), for instance, a delay circuit is used to apply anequalize pulse after the potential level of a word line has risen. Inthis case, if the supply voltage becomes high, since the charge and/ordischarge is completed at high speed in the respective logic gates, thepotential level of the equalize pulse of the SRAM falls earlier than apredetermined timing, with the result that the equalize pulse falls inlevel before the potential level status of the word line is not yetchanged, thus causing an erroneous operation.

SUMMARY OF THE INVENTION

Accordingly, the object of the present invention is to provide asemiconductor integrated circuit which can operates stably without beingsubjected to the influence of supply voltage fluctuations.

According to the present invention, a delay circuit is interposedbetween first and second circuit systems both driven by a first supplyvoltage. The delay circuit delays a signal applied by the first circuitsystem, and then transmits the delayed signal to the second circuitsystem. In the present invention, in particular a constant voltagesupply circuit generates a second supply voltage (constant voltage) onthe basis of the first supply voltage, and supplies this generatedconstant supply voltage to this delay circuit, so that a stable constantdelay time can be obtained by the delay circuit without being subjectedto the influence of fluctuations of the first supply voltage. All thecircuit elements are formed on the same semiconductor substrate.Further, it is preferable to construct the constant voltage supplycircuit in such a way that the output voltage thereof is programmable.

BRIEF DESCRIPTION OF THE DRAWINGS

In the attached drawings:

FIG. 1 is a graphical representation showing the relationship betweenthe supply voltage (Vcc) fluctuation and the delay time in a delaycircuit;

FIG. 2 is a circuit diagram showing one embodiment of the semiconductorintegrated circuit including a delay circuit according to the presentinvention;

FIG. 3 is a graphical representation showing the relationship betweenthe constant supply voltage (Vcc) and the delay time in a delay circuitshown in FIG. 2;

FIG. 4 is a circuit diagram showing another example of the delay circuitaccording to the present invention;

FIG. 5A to 5C are timing charts for assistance in explaining theoperation of the delay circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing one embodiment of a constant voltagesupply circuit shown in FIG. 2;

FIG. 7 is a detailed circuit diagram showing a programmable portionapplied to a part of the constant voltage supply circuit shown in FIG.6;

FIG. 8 is a circuit diagram showing an essential portion of the SRAM towhich the present invention is applied; and

FIGS. 9A to 9D are timing charts for assistance in explaining theoperation of the SRAM shown in FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment of the present invention will be described hereinbelowwith reference to the attached drawings. FIG. 2 shows a circuitconfiguration of an embodiment of the semiconductor integrated circuitaccording to the present invention. In FIG. 2, an input signal isapplied to a first circuit system 22. An output of the first circuitsystem 22 is given to a second circuit system 23 via a delay circuit 21.An output signal Φ is outputted from the second circuit system 23. Asupply voltage Vcc is supplied to the first and second circuit systems22 and 23 and further a constant voltage supply circuit 24,respectively. The constant voltage supply circuit 24 generates aconstant voltage Vcon on the basis of the supply voltage Vcc. Theconstant voltage Vcon of the constant voltage supply circuit 24 issupplied to the delay circuit 21. Therefore, since the delay circuit 21is activated on the basis of the constant voltage Vcon, the delay timeof the delay circuit 21 can be kept constant, without being subjected tothe influence of the fluctuations of the supply voltage Vcc, as shown inFIG. 3. In this embodiment shown in FIG. 2, the delay circuit 21 iscomposed of three series-connected inverters NOT1, NOT2 and NOT3.

FIG. 4 shows another example of the delay circuit. In this delaycircuit, an input signal In is directly applied to one input terminal 4aof a NAND gate NAND1 and to the other input terminal 4b of thereof via afive-stage inverter train composed of NOT4 to NOT8 after being delayedthrough these inverters NOT4 to 8.

The operation of the delay circuit shown in FIG. 4 will be describedhereinbelow with reference to FIGS. 5A to 5C.

Now, when a pulse of an "L" level (logical "0" level) with a time width(from t52 to t51) is inputted to the node 4a of the delay circuit, thepulse at the node 4a is directly inputted to one input terminal 4a ofthe NAND gate NAND1, and further to the other input terminal 4b of theNAND gate NAND1 after having been inverted and further delayed by adelay time Δt55 through the delay circuit composed of five invertersNOT4 to NOT8. Accordingly, both input terminals of the NAND gate NAND1change to an "H" level at timing t52, and this status is kept untiltiming t54, so that a pulse Φ of the "L" level with a time width (t54 tot52) is outputted to an output node 4c.

FIG. 6 is a circuit diagram showing an example of the constant voltagesupply circuit 24 shown in FIG. 2.

In FIG. 6, Tr1 to Tr3 are pMOS transistors for forming a current mirrorcircuit. The source of the transistor Tr1 is connected to a highpotential side supply voltage Vcc. Both the gate and the drain of thetransistor Tr1 are shorted into a diode connection. The source of thetransistor Tr2 is connected to a high potential side supply voltage Vcc.The gate of the transistor Tr2 is connected to the gate and the drain ofthe transistor Tr1, respectively. The gate of the transistor Tr3 isconnected to the drain of the transistor Tr2. This junction point 11between the gate of Tr3 and the drain of Tr2 is an input terminal Irefof the current mirror circuit. The source of the transistor Tr3 isconnected to the gate and drain of the transistor Tr1. The source of thetransistor Tr3 is an output terminal Iout of the current mirror circuit.The junction point between the drain of the transistor Tr2 and the gateof the transistor Tr3 is connected to the drain of a transistor Tr4. Thesource of this transistor Tr4 is connected to the ground voltage supplyGND. The gate of the transistor Tr4 is connected to the high potentialside supply voltage Vcc. This transistor Tr4 is a normally turned-onelement whose turn-on status changes according to the supply voltageVcc; in other words, the resistance between the source and the drain ofthe transistor Tr4 changes according to the supply voltage Vcc.

The potential at a node 10 of the junction point between the drain ofthe transistor Tr1 and the source of the transistor Tr3 can bedetermined on the basis of the ratio of the gate widths of the twotransistors Tr1 and Tr2, so that the gate-source voltage V_(GS) of thetransistor Tr3 can be held at a constant voltage and therefore thetransistor Tr3 is turned on under the condition that the source-drainresistance of the transistor Tr3 is kept at a constant level. Further,the potential at a node 11 of the common junction point between the twodrains of the two transistors Tr2 and Tr4 can be determined by theresistance ratio of both the transistors TF2 and Tr4. Here, if theturn-on status (the resistance between the source and the drain) of thetransistor Tr4 is constant, the potential at the node 11 of coursefluctuates according to the supply voltage (Vcc) fluctuations. However,since the gate of the transistor Tr4 is connected to the supply voltageVcc, the resistance between the source and the drain of the transistorTr4 changes according to the supply voltage Vcc, so that it is possibleto keep the potential of the node 11 at a constant level. In otherwords, when the turn-on status of the transistor Tr4 is kept constant,the potential at the node 11 increases with increasing supply voltageVcc, and decreased with decreasing supply voltage Vcc. However, when thesupply voltage Vcc becomes high, since the resistance between the sourceand drain of the transistor Tr4 decreases, the potential at the node 11will not increases. On the other hand, when the supply voltage Vccbecomes low, since the resistance between the source and drain of thetransistor Tr4 increases, the potential at the node 11 will notdecreases, with the result that the potential at the node 11 can be keptat a constant potential level, without being subjected to the influenceof the supply voltage (Vcc) fluctuations.

In FIG. 6, Tr5 and Tr6 are pMOS transistors for forming an activevoltage dividing circuit. The source of the transistor Tr5 is connectedto a high potential side supply voltage Vcc, and the gate thereof isconnected to the node 11. Therefore, the transistor Tr5 is activated onthe basis of the gate voltage at the node 11. The drain of thetransistor Tr5 is connected to the source of the transistor Tr6, and thegate and the drain of the transistor Tr6 are shorted and furtherconnected to the ground supply voltage GND. The potential at the node 12of the junction point between the drain of the transistor Tr5 and thesource of the transistor Tr6 is determined by the ratio of the turn-onresistances of the two transistors Tr5 and Tr6. The resistance betweenthe source and the drain of the transistor Tr5 is determined on thebasis of the constant potential at the node 11. Therefore, currentproportional to the voltage Vcc flows through the transistor Tr5, sothat a voltage drops across the transistor Tr5 in proportion to thevoltage Vcc, thus the potential at the node 12 being determined to beconstant.

In FIG. 6, Tr7 and Tr8 are nMOS transistors for forming a differentialpair. The potential at the node 12 is applied to the gate of thetransistor Tr7 as a reference voltage Vref. Tr9 and TrA are pMOStransistors for forming a current mirror circuit. The sources of the twotransistors Tr9 and TrA are connected to the high potential side supplyvoltage Vcc. The gate and the drain of the transistor Tr9 are shorted soas to form an input terminal Iref of the current mirror circuit. Thegate of the transistor TrA is connected to the gate and the drain of thetransistor Tr9, and the drain of the transistor TrA forms an outputterminal Iout of the current circuit. The drains of these transistorsTr9 and TrA are connected to the drains of two transistors Tr8 and Tr7,respectively. The current mirror circuit Tr9 and TrA form an active loadof the differential pair Tr7 and Tr8.

The common connection point between the two sources of the twotransistors Tr7 and Tr8 is connected to the drain of an nMOS TrB. Thegate of the transistor TrB is connected to the node 12 so as to bedriven by the constant reference voltage Vref. The source of thetransistor TrB is connected to the drain of an nMOS transistor TrC. Thegate of the transistor TrC is connected to the high potential sidesupply voltage Vcc and the source thereof is connected to the groundsupply voltage GND. Therefore, the resistance between the drain and thesource of the transistor TrC changes according to the supply voltageVcc, so that the potential between the high potential side supplyvoltage Vcc and the source of the transistor TrB is kept constantwithout being subjected to the fluctuations of the high potential sidesupply voltage Vcc. That is, the potential at the node 14 (the commonconnection between the sources of the differential pair Tr7 and Tr8) andthe potential at the node 15 (the connection point between the gate andthe drain of the transistor Tr9) are both determined by the ratios ofthe resistances of the three transistors Tr9, Tr8 and TrB, respectively.Accordingly, the potential at the node 13 (the connection point betweenthe drain of the transistor TrA and the drain of the transistor Tr7) canbe kept at a constant potential. To this node 13, the gate of a pMOStransistor TrD is connected. The source of the transistor TrD isconnected to the high potential side supply voltage Vcc and the drainthereof is connected to the gate of the transistor Tr8. Here, theresistance between the source and the drain of the transistor TrD isdetermined on the basis of the potential at the node 13. Therefore,current proportional to the voltage Vcc flows through the transistorTrD, so that a voltage drops across the transistor TrD in proportion tothe supply voltage Vcc. Consequently, the potential at the node 16 ofthe connection point between the drain of the transistor TrD and thegate of the transistor Tr8 is kept at a constant potential, andoutputted as an output voltage Vcon of the constant voltage supplycircuit 24.

Here, although this output voltage Vcon can be determined by thereference voltage Vref, this reference voltage Vref can be adjusted bysetting the ratio of the gate width of the two transistors Tr5 and Tr6for constituting the voltage dividing circuit 10.

The voltage dividing circuit 10 can be preferably constructed so as tobe programmable, as shown in FIG. 7. In the drawing, a plurality of pMOStransistors Tr51, . . . , Tr5n are connected between the high potentialside supply voltage Vcc and the node 12 in parallel to the transistorTr5 via fuses F1, F2, . . . , Fn, respectively. In the same way, aplurality of pMOS transistors Tr61, . . . , Tr6n are connected betweenthe node 12 and the ground supply voltage GND in parallel to thetransistor Tr6 via fuses F11, F12, . . . , F1n, respectively. Therefore,it is possible to adjust the ratio (W5/W6) (where W5 denotes the totalgate width on the Tr5 side, and W6 denotes the total gate width on theTr6 side) by selectively cutting off the fuses F1, F2, . . . , Fn andF11, F12, . . . , F1n. Therefore, any required reference voltage Vrefcan be obtained in proportion to the gate width ratio (W5/W6).

FIG. 8 is a block diagram showing an example of the present inventionapplied to a SRAM (static RAM). In the drawing, the SRAM is composed ofa pulse generating and delay circuit A1; a bit line activating circuitA2; a sense amplifier activating circuit A3; memory cells A4, A4', . . .; a sense amplifier AS; bit lines BL and/BL; word lines WL1 and WL2; anda column select line CSL. A plurality of cells A4, A4', . . . arearranged between two common bit lines BL and/BL. The sense amplifier A5is connected to these cells A4, A4', . . . through these bit lines BLand/BL in such a way that data stored in the selected cell of the cellsA4, A4', . . . can be sensed by the sense amplifier AS. Further, anequalize transistor T1 turned on or off in response to an equalize pulseis connected between the two bit lines BL and /BL.

In general, when the equalize pulse with a predetermined time width isbeing applied to the equalize transistor T1, a pair of the bit lines ofthe cell array are kept at the same potential, so that the cells can beswitched at high speed.

Here, the operation of when the word lines are switched from WL1 to WL2as shown in FIG. 9B will be described hereinbelow, under the conditionthat the two cells A4 and A4' store two complementary data,respectively.

In this case, as shown in FIG. 9A, the equalize pulse is allowed to riseat timing tc1 before the word lines are switched; that is, the selectsignal WL1 of the cell A4 is allowed to fall. Then, the equalizetransistor T1 is turned on to short the two bit lines BL and /BL, sothat the two bit lines are set to the same intermediate potential, asshown by the solid line in FIG. 9C. Thereafter, the equalize pulse isallowed to be fall at timing tc2, after the word line WL1 is switched tothe word line WL2 in potential level and further the high level of theequalize pulse is kept for a predetermined time. Then, the transistor T1is turned off, so that the potential levels of the bit lines BL and /BLare determined by the data level of the cell A4'.

Under the control as described above, the potential levels of bit linesBL and /BL change as shown by the solid lines in FIG. 9C. In contrastwith this, when not controlled by the equalize pulse, since the bitlines BL and /BL are triggered by only the switching operation of theword lines, the potentials level of the two bit lines BL and /BL changeas shown by dashed lines in FIG. 9C. FIG. 9C indicates that whencontrolled by the equalize pulse, it is possible to read data stored inthe cell A4' by a time tc3 earlier than would be the case when notcontrolled by the equalize pulse.

In other words, in the case of the conventional SRAM, as shown in FIG.9D, when the supply voltage Vcc rises, since the charge and dischargeoperation are effected at higher speed, the timing at which the equalizepulse of the SRAM falls becomes earlier than the timing tc2, as shown bytiming tc2' in FIG. 9A for instance. In this case, since the equalizepulse falls before the potential levels of the word lines WL1 and WL2change perfectly, the data stored in the cell A4 is once read by the bitlines BL and/BL and thereafter the data stored in the cell A4' is readby the bit lines BL and /BL, thus causing an erroneous operation andthereby deteriorating the reliability of the high speed data operation.

As described above, in the case where the conventional SRAM iscontrolled by the equalize pulse, if the supply voltage Vcc fluctuates,the equalize pulse is not delayed sufficiently and therefore theequalize pulse width is not sufficient, with the result that anerroneous operation may occur. In contrast with this, in the case wherethe delay circuit according to the present invention is applied to theSRAM, it is possible to stably read and write data from and in thememory cells, because the operation of the pulse generating circuit isnot subjected to the influence of the fluctuations of the supply voltageVcc.

Without being limited to only the equalize pulse generating circuit ofthe SRAM, the semiconductor integrated circuit according to the presentinvention can be applied to other pulse generating circuits forgenerating an activating signal, a write recovery signal, etc. of theinternal synchronous SRAM, for instance.

What is claimed is:
 1. A semiconductor integrated circuit, comprising:afirst circuit system supplied with a first supply voltage, for receivingan input signal; a delay circuit for delaying an output of said firstcircuit system; a second circuit system supplied with the first supplyvoltage, for generating an output in response to the output of saiddelay circuit; and a constant voltage supply circuit, supplied with thefirst supply voltage, for supplying a constant voltage to said delaycircuit, said delay circuit being supplied with only said constantvoltage, said constant voltage supply circuit further includingprogrammable means for determining a voltage value of said constantvoltage, said constant voltage supply circuit being formed on asemiconductor substrate together with said first circuit system, saiddelay circuit and said second circuit system.
 2. The semiconductorintegrated circuit as claimed in claim 1, wherein said programmablemeans comprises a voltage dividing circuit for selectively dividing saidfirst supply voltage.
 3. The semiconductor integrated circuit as claimedin claim 2, wherein said voltage dividing circuit comprises:a group ofhigh potential side MOS transistors each having a source and a drainconnected between a supply point of the first supply voltage and avoltage dividing point, respectively, so as to function as highpotential side active resistance elements; a group of low potential sideMOS transistors each having a source and a drain connected between thevoltage dividing point and a ground, respectively so as to function aslow potential side active resistance elements; a group of high potentialside fuses each providing a connection between the voltage dividingpoint and a transistor of said high potential side MOS transistor group,said fuses selectively cutting off connections between the voltagedividing point and transistors of said high potential side MOStransistor group; and a group of low potential side fuses each providinga connection between the voltage dividing point and a transistor of saidlow potential side MOS transistor group, said fuses selectively cuttingoff connections between the voltage dividing point and transistors ofsaid low potential side MOS transistor group.
 4. The semiconductorintegrated circuit as claimed in 2, which further comprises adifferential amplifier for outputting an amplified output on the basisof a reference voltage outputted by said voltage dividing circuit.